Deutsch
Deutschland
Anmelden
Tipp von eurobuch.com
Ähnliche Bücher
Weitere, andere Bücher, die diesem Buch sehr ähnlich sein könnten:
Buch verkaufen
Anbieter, die das Buch mit der ISBN 9781441909497 ankaufen:
Suchtools
Buchtipps
Aktuelles
FILTER
- 0 Ergebnisse
Kleinster Preis: 110,73 €, größter Preis: 180,31 €, Mittelwert: 146,24 €
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri:
Minimizing and Exploiting Leakage in VLSI Design - neues Buch

ISBN: 9781441909497

ID: 618814a823586f881a52a66c86ff8826

This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. Bücher / Fremdsprachige Bücher / Englische Bücher 978-1-4419-0949-7, Springer

Neues Buch Buch.de
Nr. 17593450 Versandkosten:Bücher und alle Bestellungen die ein Buch enthalten sind versandkostenfrei, sonstige Bestellungen innerhalb Deutschland EUR 3,-, ab EUR 20,- kostenlos, Bürobedarf EUR 4,50, kostenlos ab EUR 45,-, Sofort lieferbar, más costos de envío, zzgl. Versandkosten
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Nikhil Jayakumar#Suganth Paul#Rajesh Garg#Kanupriya Gulati#Sunil P. Khatri:
Minimizing and Exploiting Leakage in VLSI Design - neues Buch

ISBN: 9781441909497

ID: 7200646

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. This book presents two techniques to reduce leakage power in digital VLSI ICs. The first reduces leakage through the selective use of high threshold voltage sleep transistors, while the second by applying the optimal Reverse Body Bias voltage. Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, Springer

Neues Buch Thalia.de
No. 17593450 Versandkosten:, Sofort lieferbar, DE (EUR 0.00)
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Minimizing and Exploiting Leakage in VLSI Design - Jayakumar, Nikhil / Paul, Suganth / Garg, Rajesh
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Jayakumar, Nikhil / Paul, Suganth / Garg, Rajesh:
Minimizing and Exploiting Leakage in VLSI Design - gebrauchtes Buch

ISBN: 9781441909497

ID: 6748512

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. Minimizing and Exploiting Leakage in VLSI Design Jayakumar, Nikhil / Paul, Suganth / Garg, Rajesh, Springer

gebrauchtes bzw. antiquarisches Buch Betterworldbooks.com
Versandkosten: EUR 0.00
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Nikhil Jayakumar:
Minimizing and Exploiting Leakage in VLSI Design - neues Buch

ISBN: 9781441909497

[ED: Buch], [PU: Springer-Verlag GmbH], Neuware - Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic. -, [SC: 0.00], Neuware, gewerbliches Angebot, 243x155x23 mm, [GW: 510g]

Neues Buch Booklooker.de
Sparbuchladen
Versandkosten:Versandkostenfrei, Versand nach Deutschland (EUR 0.00)
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.
Minimizing and Exploiting Leakage in VLSI Design - Nikhil Jayakumar
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Nikhil Jayakumar:
Minimizing and Exploiting Leakage in VLSI Design - neues Buch

ISBN: 9781441909497

[ED: Buch], [PU: Springer-Verlag GmbH], Neuware - Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic., [SC: 0.00], Neuware, gewerbliches Angebot, 243x155x23 mm, [GW: 510g]

Neues Buch Booklooker.de
Carl Hübscher GmbH
Versandkosten:Versandkostenfrei, Versand nach Deutschland (EUR 0.00)
Details...
(*) Derzeit vergriffen bedeutet, dass dieser Titel momentan auf keiner der angeschlossenen Plattform verfügbar ist.

Details zum Buch
Minimizing and Exploiting Leakage in VLSI Design

Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the increasing demand for portable/hand-held electronics, has made power consumption a dominant concern in the design of VLSI circuits today. Traditionally, dynamic (switching) power has dominated the total power consumption of an IC. However, due to current scaling trends, leakage power has now become a major component of the total power consumption in VLSI circuits. Leakage power reduction is especially important in portable/hand-held electronics such as cell-phones and PDAs. This book presents two techniques aimed at reducing leakage power in digital VLSI ICs. The first technique reduces leakage through the selective use of high threshold voltage sleep transistors. The second technique reduces leakage by applying the optimal Reverse Body Bias (RBB) voltage. This book also shows readers how to turn the leakage problem into an opportunity, through the use of sub-threshold logic.

Detailangaben zum Buch - Minimizing and Exploiting Leakage in VLSI Design


EAN (ISBN-13): 9781441909497
ISBN (ISBN-10): 1441909494
Gebundene Ausgabe
Erscheinungsjahr: 2010
Herausgeber: Springer-Verlag GmbH
214 Seiten
Gewicht: 0,510 kg
Sprache: eng/Englisch

Buch in der Datenbank seit 17.12.2007 05:54:55
Buch zuletzt gefunden am 15.05.2017 10:56:10
ISBN/EAN: 9781441909497

ISBN - alternative Schreibweisen:
1-4419-0949-4, 978-1-4419-0949-7


< zum Archiv...
Benachbarte Bücher