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Digit-Serial Computation (Hardback) - Richard Hartley, Keshab K. Parhi
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Richard Hartley, Keshab K. Parhi:
Digit-Serial Computation (Hardback) - gebunden oder broschiert

1995, ISBN: 0792395735

ID: 11220955323

[EAN: 9780792395737], Neubuch, [PU: Kluwer Academic Publishers, United States], Technology|Electricity, Technology|Electronics|Circuits|General, Technology|Engineering|Electrical, Language: English . Brand New Book ***** Print on Demand *****. Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real- time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit- serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory.

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[ED: Hardcover], [PU: Springer, Berlin], Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descriptions. An implementation of this design methodology, the Parsifal silicon compiler was developed at the General Electric Corporate Research and Development laboratory. xiii, 306 S. XIII, 306 p. 235 mm Versandfertig in 3-5 Tagen, DE, [SC: 0.00], Neuware, gewerbliches Angebot, offene Rechnung (Vorkasse vorbehalten)

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Digit-Serial Computation (The Springer International Series in Engineering and Computer Science) - Richard Hartley; Keshab Parhi
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Digit-Serial Computation (The Springer International Series in Engineering and Computer Science) - gebrauchtes Buch

ISBN: 0792395735

ID: 6952621

Digital signal processing (DSP) is used in a wide range of applications such as speech, telephone, mobile radio, video, radar and sonar. The sample rate requirements of these applications range from 10 KHz to 100 MHz. Real time implementation of these systems requires design of hardware which can process signal samples as these are received from the source, as opposed to storing them in buffers and processing them in batch mode. Efficient implementation of real­ time hardware for DSP applications requires study of families of architectures and implementation styles out of which an appropriate architecture can be selected for a specified application. To this end, the digit-serial implementation style is proposed as an appropriate design methodology for cases where bit-serial systems cannot meet the sample rate requirements, and bit-parallel systems require excessive hardware. The number of bits processed in a clock cycle is referred to as the digit-size. The hardware complexity and the achievable sample rate increase with increase in the digit-size. As special cases, a digit­ serial system is reduced to bit-serial or bit-parallel when the digit-size is selected to equal one or the word-length, respectively. A family of implementations can be obtained by changing the digit-size parameter, thus permitting an optimal trade-off between throughput and size. Because of their structured architecture, digit-serial designs lend themselves to automatic compilation from algorithmic descr computer design,computers and technology,electrical and electronics,engineering,mathematics,microprocessors and system design,science and math Mathematics, Springer

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Digit-Serial Computation - Richard Hartley, Keshab Parhi
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ISBN: 9780792395737

ID: 978079239573

The sampling rates for digital signal processing (DSP) in such applications as speech, telephony, mobile radio, video, radar and sonar, ranges from 10 kHz to 100 MHz. Real-time implementation of such systems requires design of hardware that can process signal samples as these are received from the source, rather than storing them in buffers for batch-mode processing. Efficient implementation of DSP hardware demands a study of families of architectures and styles, selecting an appropriate architecture for a specific application. Digit-Serial Computation is proposed as an appropriate design methodology when bit-serial systems cannot meet sampling rate requirements, and where bit-parallel systems require excessive hardware. A family of implementations can be obtained by changing the digit size parameter, allowing an optimum trade-off between throughput and size. Digit-Serial Computation describes the architecture, and the design and layout methods used in Parsifal: the silicon compiler developed at GEC''s Corporate R&D Laboratory. The structures architecture of digit-serial designs lends itself to automatic compilation from algorithmic descriptions. The book also goes on to discuss wider-ranging issues in digit-serial design in chapters on `folding'' and `unfolding'', as well as in chapters on systolic arrays, canonic-signed-digit number representation and carry-save arithmetic. The book is an excellent source of reference and may be used as a text for an advanced course on the subject. Richard Hartley, Keshab Parhi, Books, Science and Nature, Digit-Serial Computation Books>Science and Nature, Springer US

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Digit-Serial Computation (The Springer International Series in Engineering and Computer Science) - Hartley, Richard; Parhi, Keshab
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Hartley, Richard; Parhi, Keshab:
Digit-Serial Computation (The Springer International Series in Engineering and Computer Science) - gebunden oder broschiert

1995, ISBN: 0792395735

ID: 19184933592

[EAN: 9780792395737], Neubuch, [PU: Springer], Technology|Electricity, Technology|Electronics|Circuits|General, Technology|Engineering|Electrical, This item is printed on demand for shipment within 3 working days.

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Details zum Buch
Digit-Serial Computation

The sampling rates for digital signal processing (DSP) in such applications as speech, telephony, mobile radio, video, radar and sonar, ranges from 10 kHz to 100 MHz. Real-time implementation of such systems requires design of hardware that can process signal samples as these are received from the source, rather than storing them in buffers for batch-mode processing. Efficient implementation of DSP hardware demands a study of families of architectures and styles, selecting an appropriate architecture for a specific application. Digit-Serial Computation is proposed as an appropriate design methodology when bit-serial systems cannot meet sampling rate requirements, and where bit-parallel systems require excessive hardware. A family of implementations can be obtained by changing the digit size parameter, allowing an optimum trade-off between throughput and size. Digit-Serial Computation describes the architecture, and the design and layout methods used in Parsifal: the silicon compiler developed at GEC's Corporate R&D Laboratory. The structures architecture of digit-serial designs lends itself to automatic compilation from algorithmic descriptions. The book also goes on to discuss wider-ranging issues in digit-serial design in chapters on `folding' and `unfolding', as well as in chapters on systolic arrays, canonic-signed-digit number representation and carry-save arithmetic. The book is an excellent source of reference and may be used as a text for an advanced course on the subject.

Detailangaben zum Buch - Digit-Serial Computation


EAN (ISBN-13): 9780792395737
ISBN (ISBN-10): 0792395735
Gebundene Ausgabe
Erscheinungsjahr: 1995
Herausgeber: Springer-Verlag GmbH
324 Seiten
Gewicht: 0,649 kg
Sprache: eng/Englisch

Buch in der Datenbank seit 02.03.2008 02:52:48
Buch zuletzt gefunden am 18.06.2017 15:37:04
ISBN/EAN: 9780792395737

ISBN - alternative Schreibweisen:
0-7923-9573-5, 978-0-7923-9573-7


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