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Code Based Test Data Compression for SoC Testing: Optimization of Time, Power and Area Overhead - Usha Sandeep Mehta, K. S. Dasgupta, N. M. Devashrayee
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Usha Sandeep Mehta, K. S. Dasgupta, N. M. Devashrayee:

Code Based Test Data Compression for SoC Testing: Optimization of Time, Power and Area Overhead - Taschenbuch

ISBN: 3848486318

[SR: 10567463], Paperback, [EAN: 9783848486311], LAP LAMBERT Academic Publishing, LAP LAMBERT Academic Publishing, Book, [PU: LAP LAMBERT Academic Publishing], LAP LAMBERT Academic Publishing, To handle design complexity and short time-to-market, it has been common to use modular design approach in SoC. Such IP cores with hidden architecture have exaggerated the burning issues for fabrication testing of SoC: the test cost and test power. The cost of test is strongly related to the increasing test-data volumes which lead to longer test application times and larger tester memory. The solution is test data compression. The increasing test power leads to system reliability issues. The dynamic power which is is directly related to the number of transitions during scan operations plays a major role in overall test power. In this book, the ‘test data compression’ and ‘switching activity reduction’ in context of ‘IP cores’ are addressed. For ATPG generated binary data with large number of don’t care bits, ‘run length codes’ and ‘statistical codes’ are most suitable for IP cores. The switching activity reduction for external testing is suitable to IP cores for power reduction. If the ‘don’t care bit filling’ and ‘reordering’ are used in synergy to pre-process the test data, the compression and p, 13443, Astronomy, 13439, Astronomy & Space Science, 75, Science & Math, 1000, Subjects, 283155, Books

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ISBN: 9783848486311

ID: 44ee2832a24fc79a0dc6f695140a9393

Optimization of Time, Power and Area Overhead To handle design complexity and short time-to-market, it has been common to use modular design approach in SoC. Such IP cores with hidden architecture have exaggerated the burning issues for fabrication testing of SoC: the test cost and test power. The cost of test is strongly related to the increasing test-data volumes which lead to longer test application times and larger tester memory. The solution is test data compression. The increasing test power leads to system reliability issues. The dynamic power which is is directly related to the number of transitions during scan operations plays a major role in overall test power. In this book, the 'test data compression' and 'switching activity reduction' in context of 'IP cores' are addressed. For ATPG generated binary data with large number of don't care bits, 'run length codes' and 'statistical codes' are most suitable for IP cores. The switching activity reduction for external testing is suitable to IP cores for power reduction. If the 'don't care bit filling' and 'reordering' are used in synergy to pre-process the test data, the compression and power issues can be addressed without much on-chip area overhead. Bücher / Fremdsprachige Bücher / Englische Bücher 978-3-8484-8631-1, LAP Lambert Academic Publishing

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Code Based Test Data Compression for SoC Testing - N. M. Devashrayee#K. S. Dasgupta#Usha Sandeep Mehta
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Code Based Test Data Compression for SoC Testing - neues Buch

ISBN: 9783848486311

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To handle design complexity and short time-to-market, it has been common to use modular design approach in SoC. Such IP cores with hidden architecture have exaggerated the burning issues for fabrication testing of SoC: the test cost and test power. The cost of test is strongly related to the increasing test-data volumes which lead to longer test application times and larger tester memory. The solution is test data compression. The increasing test power leads to system reliability issues. The dynamic power which is is directly related to the number of transitions during scan operations plays a major role in overall test power. In this book, the ´test data compression´ and ´switching activity reduction´ in context of ´IP cores´ are addressed. For ATPG generated binary data with large number of don´t care bits, ´run length codes´ and ´statistical codes´ are most suitable for IP cores. The switching activity reduction for external testing is suitable to IP cores for power reduction. If the ´don´t care bit filling´ and ´reordering´ are used in synergy to pre-process the test data, the compression and power issues can be addressed without much on-chip area overhead. Optimization of Time, Power and Area Overhead Buch (fremdspr.) Bücher>Fremdsprachige Bücher>Englische Bücher, LAP Lambert Academic Publishing

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Code Based Test Data Compression for SoC Testing - Usha Sandeep Mehta, K.S. Dasgupta, N.M. Devashrayee
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Usha Sandeep Mehta, K.S. Dasgupta, N.M. Devashrayee, Paperback, English-language edition, Pub by AV Akademikerverlag GmbH & Co. KG. Books, Science~~Astronomy, Code-Based-Test-Data-Compression-for-SoC-Testing~~Usha-Sandeep-Mehta, 999999999, Code Based Test Data Compression for SoC Testing, Usha Sandeep Mehta, K.S. Dasgupta, N.M. Devashrayee, 3848486318, AV Akademikerverlag GmbH & Co. KG., , , , , AV Akademikerverlag GmbH & Co. KG.

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Code Based Test Data Compression for Soc Testing - Taschenbuch

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Code Based Test Data Compression for SoC Testing
Autor:

Mehta, Usha Sandeep / Dasgupta, K. S. / Devashrayee, N. M.

Titel:

Code Based Test Data Compression for SoC Testing

ISBN-Nummer:

9783848486311

Detailangaben zum Buch - Code Based Test Data Compression for SoC Testing


EAN (ISBN-13): 9783848486311
ISBN (ISBN-10): 3848486318
Gebundene Ausgabe
Taschenbuch
Erscheinungsjahr: 2012
Herausgeber: LAP Lambert Academic Publishing

Buch in der Datenbank seit 25.05.2008 20:01:00
Buch zuletzt gefunden am 17.07.2016 13:13:36
ISBN/EAN: 9783848486311

ISBN - alternative Schreibweisen:
3-8484-8631-8, 978-3-8484-8631-1

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