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Techniques to Mitigate the Effects of Congenital Faults in Processors - Smruti Sarangi
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Smruti Sarangi:

Techniques to Mitigate the Effects of Congenital Faults in Processors - Taschenbuch

ISBN: 9783639046373

[ED: Taschenbuch], [PU: VDM Verlag Dr. Müller e.K.], Neuware - It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation. - - Besorgungstitel - vorauss. Lieferzeit 3-5 Tage., [SC: 0.00], Neuware, gewerbliches Angebot, 220x150x10 mm, [GW: 255g]

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Techniques to Mitigate the Effects of Congenital Faults in Processors - Smruti Sarangi
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Smruti Sarangi:

Techniques to Mitigate the Effects of Congenital Faults in Processors - Taschenbuch

2013, ISBN: 3639046374

ID: 9734095516

[EAN: 9783639046373], Neubuch, [PU: VDM Verlag Dr. Müller E.K. Okt 2013], This item is printed on demand - Print on Demand Titel. Neuware - It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation. 160 pp. Englisch

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Techniques to Mitigate the Effects of Congenital Faults in Processors - Smruti Sarangi
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Smruti Sarangi:
Techniques to Mitigate the Effects of Congenital Faults in Processors - Taschenbuch

ISBN: 9783639046373

[ED: Taschenbuch], [PU: VDM Verlag Dr. Müller e.K.], Neuware - It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation., [SC: 0.00], Neuware, gewerbliches Angebot, 220x150x10 mm, [GW: 255g]

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Techniques to Mitigate the Effects of Congenital Faults in Processors - Smruti Sarangi
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Smruti Sarangi:
Techniques to Mitigate the Effects of Congenital Faults in Processors - Taschenbuch

ISBN: 9783639046373

[ED: Taschenbuch], [PU: VDM Verlag Dr. Müller e.K.], Neuware - It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation., [SC: 0.00], Neuware, gewerbliches Angebot, 220x150x10 mm, [GW: 255g]

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Techniques to Mitigate the Effects of Congenital Faults in Processors - Sarangi, Smruti Torrellas, Josep
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Sarangi, Smruti Torrellas, Josep:
Techniques to Mitigate the Effects of Congenital Faults in Processors - Taschenbuch

2008, ISBN: 9783639046373

[ED: Softcover], [PU: Vdm Verlag Dr. Müller], It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation.2008. 160 S. 220 mmVersandfertig in 3-5 Tagen, [SC: 0.00]

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Techniques to Mitigate the Effects of Congenital Faults in Processors
Autor:

Sarangi, Smruti; Torrellas, Josep

Titel:

Techniques to Mitigate the Effects of Congenital Faults in Processors

ISBN-Nummer:

3639046374

It is getting increasingly difficult to verify processors and guarantee subsequent reliable operation. The complexity of processors is rapidly increasing with every new generation, leading to an increase in the number of design defects, ie. logical bugs in RTL. Simultaneously, with every new generation, process variations are making it tougher to ensure timing closure, leading to an increased susceptibility to timing faults. In this thesis we characterize and propose solutions to mitigate the effects of such congenital faults. We characterize RTL defects for 10 state of the art processors. Subsequently, we find common patterns and design an architecture to avoid such faults from manifesting. The process of testing for such defects is compounded by the fact that we have non-determinism in modern processors. We propose an architecture, CADRE, to remove most sources of non-determinism, and to allow of deterministic replay of faults. To redress the problem of process variation we propose a model of how parameter variation affects timing errors. We design a fuzzy logic based architecture that tries to maximize performance in the face of timing errors due to process variation.

Detailangaben zum Buch - Techniques to Mitigate the Effects of Congenital Faults in Processors


EAN (ISBN-13): 9783639046373
ISBN (ISBN-10): 3639046374
Taschenbuch
Erscheinungsjahr: 2008
Herausgeber: VDM Verlag
160 Seiten
Gewicht: 0,255 kg
Sprache: eng/Englisch

Buch in der Datenbank seit 24.01.2009 13:22:02
Buch zuletzt gefunden am 21.09.2016 15:19:06
ISBN/EAN: 3639046374

ISBN - alternative Schreibweisen:
3-639-04637-4, 978-3-639-04637-3

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