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Latchup - Steven H. Voldman
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Steven H. Voldman:

Latchup - neues Buch

ISBN: 9780470516164

ID: 9780470516164

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers,  and buried grids – from single- to triple-well CMOS   practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha  (a) space, beta (b) space, new latchup design methods– connecting the theoretical to the practical analysis, and examples of  latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design,  to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author’ s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology.  Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration. Latchup: Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers,  and buried grids – from single- to triple-well CMOS   practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha  (a) space, beta (b) space, new latchup design methods– connecting the theoretical to the practical analysis, and examples of  latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design,  to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author’ s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology.  Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration. Circuit Theory & Design Electrical & Electronics Engineering Elektrotechnik u. Elektronik Halbleiter Halbleitertechnik Schaltkreise - Theorie u. Entwurf Semiconductors, John Wiley & Sons

Neues Buch Rheinberg-Buch.de
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Latchup - Steven H. Voldman
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)

Steven H. Voldman:

Latchup - neues Buch

ISBN: 9780470516164

ID: 9780470516164

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers,  and buried grids – from single- to triple-well CMOS   practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha  (a) space, beta (b) space, new latchup design methods– connecting the theoretical to the practical analysis, and examples of  latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design,  to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author’ s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology.  Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration. Latchup: Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration.Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand.This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as:latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers,  and buried grids – from single- to triple-well CMOS   practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha  (a) space, beta (b) space, new latchup design methods– connecting the theoretical to the practical analysis, and examples of  latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design,  to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level.Latchup acts as a companion text to the author’ s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and system-level ESD engineer. Semiconductor device, process and circuit designers, and quality, reliability and failure analysis engineers will find it informative on the issues that confront modern CMOS technology.  Practitioners in the automotive and aerospace industries will also find it useful. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, computer aided design and design integration. Halbleitertechnik Circuit Theory & Design Semiconductors Elektrotechnik u. Elektronik Electrical & Electronics Engineering Schaltkreise - Theorie u. Entwurf Halbleiter, John Wiley & Sons

Neues Buch Rheinberg-Buch.de
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Latchup - Voldman, Steven H.
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Voldman, Steven H.:
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2008

ISBN: 047051616X

ID: 9780470516164

In englischer Sprache. Verlag: John Wiley & Sons, Steven H. Voldman is an IEEE Fellow for 'Contributions inESD Protection in CMOS, Silicon on Insulator and Silicon GermaniumTechnology'. He has a B.S. engineering science from University ofBuffalo (1979), a first M.S. EE (1981) from Massachusetts Instituteof Technology (MIT), a second EE degree (engineering degree) fromMIT,a M.S. in engineering physics (1986) and a Ph.D. EE (1991) fromUniversity of Vermont under IBM's Resident Study Fellow Program. Since 1984, Voldman has provided experimental research,invention, chip design integration, circuit design, customersupport and strategic planning for ESD and latchup. His latchup andESD work consist of pioneering work on advanced CMS and BiCMOSsemiconductor processing, and presently he is working on RF CMOS,RF BiCMOS silicon germanium (SiGe) technology, image processing andhigh-voltage smart power technology. Dr Voldman has written over 150 technical papers between 1982and 2007. He is a recipient of over 160 issued US patents and 80 USpatents are pending, in the area of ESD and CMOS latchup, DrVoldman is an author of the John Wiley & Sons ESD book series -the first book, ESD: Physics and Devices; the second book, ESD:Circuits and Devices; and the third book, ESD: RF Technology andCircuits - as well as a contri8butor to the book, SiliconGermanium: Technology, Modeling and Design. Dr. Voldman waschairman of the SEMATECHESD Working Group from 1995 to 2000, toestablish a national strategy for ESD in the United Sates; thisgroup initiated ESD technology benchmarking strategy, teststructures and commercial test system strategy. Dr Voldman was alsopart of the SEMATECH vertical modulated well PTAB in 1992that focused on MeV implantation of latchup. He is a member of theESD Association Board of Directors, ESDA Education Committee, aswell ESD Standards Chairman for Transmission Line Pulse (TLP) andVery Fast TLP (VF-LP) testing committee. He has served on variousSymposia internationally from technical program committee totutorials on ESD and latchup - EOS/ESD Symposium, InternationalReliability Physics (IRPS), Taiwan ESSD Symposium (T-ESDC),International Conference on Electromagnetic Compatibility (ICEMAC),International Physical and Failure Analysis (IPFA) Symposium andBipolar/BiCMOS Circuit Technology Meeting (BCTM). Steve Voldman Initiated the 'ESD on Campus' program to bring ESDlectures and interaction to university faculty and studentsinternationally and has provided lectures in the United States,Europe, Taiwan, Singapore, Malaysia, Philippines, China andThailand. Dr. Voldman received the ESD Association OutstandingContribution Award in 2007. PC-PDF, 472 Seiten, 472 Seiten, 1., Auflage, [GR: 9684 - Nonbooks, PBS / Technik/Elektronik, Elektrotechnik, Nachrichtentechnik], [SW: - Anlagenbau Elektronik und Nachrichtentechnik (Kommunikationstechnik)], [Ausgabe: 1][PU:John Wiley & Sons], [PU: Wiley]

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Latchup - Wiley
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Latchup - neues Buch

2008, ISBN: 9780470516164

ID: 5577729

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as: latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods connecting the theoretical to the practical analysis, and; examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level. Latchup acts as a companion text to the author s series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference for the professional semiconductor chip and s. eBooks, , Latchup~~EBook~~9780470516164~~Steven H. Voldman, , Latchup, Steven H. Voldman, 9780470516164, Wiley, 04/15/2008, , , , Wiley

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Latchup - Wiley
Vergriffenes Buch, derzeit bei uns nicht verfügbar.
(*)
Wiley:
Latchup - neues Buch

2008, ISBN: 9780470516164

ID: 5577729

Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This. Interest in latchup is being renewed with the evolution of complimentary metal-oxide semiconductor (CMOS) technology, metal-oxide-semiconductor field-effect transistor (MOSFET) scaling, and high-level system-on-chip (SOC) integration. Clear methodologies that grant protection from latchup, with insight into the physics, technology and circuit issues involved, are in increasing demand. This book describes CMOS and BiCMOS semiconductor technology and their sensitivity to present day latchup phenomena, from basic over-voltage and over-current conditions, single event latchup (SEL) and cable discharge events (CDE), to latchup domino phenomena. It contains chapters focusing on bipolar physics, latchup theory, latchup and guard ring characterization structures, characterization testing, product level test systems, product level testing and experimental results. Discussions on state-of-the-art semiconductor processes, design layout, and circuit level and system level latchup solutions are also included, as well as: latchup semiconductor process solutions for both CMOS to BiCMOS, such as shallow trench, deep trench, retrograde wells, connecting implants, sub-collectors, heavily-doped buried layers, and buried grids - from single- to triple-well CMOS; practical latchup design methods, automated and bench-level latchup testing methods and techniques, latchup theory of logarithm resistance space, generalized alpha (a) space, beta (b) space, new latchup design methods- connecting the theoretical to the practical analysis, and; examples of latchup computer aided design (CAD) methodologies, from design rule checking (DRC) and logical-to-physical design, to new latchup CAD methodologies that address latchup for internal and external latchup on a local as well as global design level. Latchup acts as a companion text to the author's series of books on ESD (electrostatic discharge) protection, serving as an invaluable reference f. eBooks, , Latchup~~EBook~~9780470516164~~Steven H. Voldman, , Latchup, Steven H. Voldman, 9780470516164, Wiley, 04/15/2008, , , , Wiley

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Latchup
Autor:

Voldman, Steven H.

Titel:

Latchup

ISBN-Nummer:

047051616X

Detailangaben zum Buch - Latchup


EAN (ISBN-13): 9780470516164
ISBN (ISBN-10): 047051616X
Erscheinungsjahr: 2008
Herausgeber: Wiley, J
472 Seiten
Sprache: eng/Englisch

Buch in der Datenbank seit 10.01.2009 21:04:30
Buch zuletzt gefunden am 25.01.2016 03:02:18
ISBN/EAN: 047051616X

ISBN - alternative Schreibweisen:
0-470-51616-X, 978-0-470-51616-4

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